Command Structure

ALL ABOUT THE GENERAL PURPOSE DDS PROJECT

Initially April 2011 Alan Stummer astummer-at-physics.utoronto.ca
Based on ChromaMatic2 project.
This project uses the AD9110 DDS eval board, an Altera Cyclone III FPGA and the Rabbit RCM4200.

** HOST IP DESCRIPTION **
- Format is UDP on port 37829
- Unit "GP-DDS #1" IP address is 192.168.1.154
- Every time unit is turned on, first host to connect is the only one allowed to send commands
- Host sends commands as listed below
- Every second or so, host sends a heartbeat and the unit echoes it, harmless if not sent

** MONITOR IP DESCRIPTION **
- The program Warren performs the monitor functions, run on one or more computers on the same subnet.
- Format is UDP on port 6595
- Units broadcast messages on xxx.xxx.xxx.255
- Units send text messages about status
- Some older units also send data
- Monitor simply time stamps and records them verbatum
- Messages have unit's name in message
- Keywords "Warning: and "ERROR:", self-descriptive.

** HOST COMMANDS **

CMD Size Description


0x7F 1 Heartbeat, tells unit host is connected, and vice versa when unit echos HB
0xA4 1 Wait for Adwin trigger (can't use here, only in command sequence)
0xA8 1 Wait for ramp to end (can't use here, only in command sequence)
0xA5 6 Set the FTW (Freq Tuning Word)
byte 1: 0xA5
2: don't care (back compatibility)
3 to 6: LS to MS FTW bytes
0xAB 1 Freeze a DDS ramp now, if it happens to be ramping
0xAC 16 Initiate DDS ramping
byte 1: 0xAC
2 to 3: ignored (LS bytes of Digital Ramp Step Size)
4 to 7: Digital Ramp Step Size, LS to MS bytes
8: ignored (LS byte of DR Rate)
9 to 10: DR Rate, LS to MS bytes
11 to 12: ignored (LS bytes of Stop Freq)
13 to 16: Stop Freq, LS to MS bytes
0xC0 1 Clear the command sequence, reset pointers
0xC1 1 Following command is to be added to command sequence (see note below)
0xC4 2 Begin execution of the command sequence
0xC5 1 Restart the existing command sequence (grandfathered, same as 0xC4?)
0xEE 1 Get test debug byte (used for debugging only, byte defined by FPGA code)
NOTE: A command preceded by 0xC1 means to store that command in the command sequence.
Example: 0xC1 A4 when executed in cmd seq means wait for Trigger before executing next cmd


END OF HOST INFORMATION *
FOLOWING IS FOR DYNAMIC C AND VERILOG DEVELOPMENT ONLY
**

Note that little or no error checking on commands from Rabbit is done, it is assumed that
there are no errors. If errors are sent, they will have unknown results.

*** Following commands can be executed by the Rabbit directly
CMD Description


0xA5 Set the FTW (Freq Tuning Word)
0xAB Freeze a DDS ramp now, if it happens to be ramping
0xC0 1 Clear the command sequence, reset pointers
0xC1 1 Following command is to be added to command sequence (see note below)
0xC4 2 Begin execution of the command sequence
0xC5 1 Restart the existing command sequence (grandfathered, same as 0xC4?)

0x7F 1 Heartbeat, tells unit host is connected, and vice versa when unit echos HB
0xA4 1 Wait for Adwin trigger (can't use here, only in command sequence)

*** Following commands can be loaded into the cmd seq
CMD Description


0xA5 Set the FTW (Freq Tuning Word)
0xAB Freeze a DDS ramp now, if it happens to be ramping
0xAC Initiate DDS ramping
0xA4 Wait for Adwin trigger before executing next command

The cmd seq holds sequential commands for the DDS registers in the FPGA. Before running they
are loaded into the FPGA by the Rabbit. At runtime they are pushed intothe DDS when
requested. The cmd seq is one long byte string. There are three types of cmd seq records:
1) PROGRAM A DDS REGISTER. These cmd seq records have 3 fields:
1 byte of record size (excludes itself, includes reg address and data)
1 byte of the DDS register address
x bytes of data for the DDS register
2) SET THE STATE OF A DDS HARDWARE PIN including IOReset, IOUpdate, DRHold and DRCtrl pins.
These cmd seq records have 2 fields:
1 byte 0x01, to indicate that a hardware pin is to be set
1 byte of which pin and state
3) WAIT FOR A TRIGGER INPUT rising edge before continuing.
This cmd seq record has 2 fields:
1 byte 0x01, to indicate that it is a 1 byte command
1 byte of 0xC1

** RABBIT COMMANDS TO FPGA **
Note: Commands are only valid when FPGA CS (PB5) is high
CMD Description


0x0 Serial write direct to DDS registers (see DDS Register Table below)
0x1 Reset command sequence
0x2 Return to start of command sequence but do not run it
0x3 Start running command sequence (stops when reset or ran last command)
0x4 Add a byte to command sequence
0x5 not used
0x6 not used
0x7 Read FPGA version (4-bit MS, 4-bit LS, big endian)
0x8-E not used
0xF Read test debug byte (as set in FPGA).

** HARDWARE PIN COMMANDS TO ADD TO COMMAND SEQUENCE **
Note: These are added into the cmd seq as "0x01 nn" where nn is the command.
CMD Description


0x01 Set IO Reset pin low
0x02 Set IO Reset pin high (clear serial interface)
0x03 Set IO Update pin low
0x04 Set IO Update pin high (updates the buffered data0
0x05 Set DR Hold pin low
0x06 Set DR Hold pin high (freezes a digital ramp)
0x07 Set DR Ctrl pin low (ramp down)
0x08 Set DR Ctrl pin high (ramp up)
0xA4 Wait for trigger input (ref, shown above)
0xA8 Wait for ramp to end (ref, shown above)

** RABBIT RCM4200 PORT MAPPING **
PORT DIR DESCRIPTION


PA0 I/O FPGA D0; with Cmd 0x0, output to DDS IO_RESET
PA1 I/O FPGA D1; with Cmd 0x0, output to DDS SCLK
PA2 I/O FPGA D2; with Cmd 0x0, output to DDS SDIO
PA3 I/O FPGA D3; with Cmd 0x0, output to DDS RESET
PA4 I/O FPGA D4; with Cmd 0x0, output to DDS IOUPDATE
PA5 I/O FPGA D5; with Cmd 0x0, output to DDS DRHOLD
PA6 I/O FPGA D6; with Cmd 0x0, output to DDS DRCTRL
PA7 I/O FPGA D7

PB0 - (onboard ADC SCLK)
PB1 O FPGA Cmd0
PB2 O FPGA Cmd1
PB3 O FPGA Cmd2
PB4 O FPGA Cmd3
PB5 O FPGA CS
PB6 - FPGA Spare 0 (can be future SDO from DDS)
PB7 - FPGA Spare 1

PC0 O Display data
PC1 -
PC2 -
PC3 -
PC4 - (onboard ADC SDI)
PC5 - (onboard ADC SDO)
PC6 -
PC7 -

PD0-7 - (onboard ADC inputs)

PE0 - FPGA Spare 2
PE1 -
PE3 -
PE4 I Cmd Seq Overflow

** DDS Register Table **
Reg Add Size DESCRIPTION (size is in bytes)


CFR1 0x00 4 Control Function Reg 1
CFR2 0x01 4 Control Function Reg 2
CFR3 0x02 4 Control Function Reg 3
ADCR 0x03 4 Auxilliary DAC Control Reg
IOUR 0x04 4 I/O Update Rate
FTW 0x07 4 Frequency Tuning Word
POW 0x08 4 Phase Offset Word
ASF 0x09 4 Amplitude Scale Factor
MCS 0x0A 4 Multi-Chip Sync
DRL 0x0B 8 Digital Ramp Limit
DRS 0x0C 8 Digital Ramp Step
DRR 0x0D 4 Digital Ramp Rate
STP0 0x0E 8 Single Tone Profile 0
RP0 0x0E 8 RAM Profile 0
STP1 0x0F 8 Single Tone Profile 1
RP1 0x0F 8 RAM Profile 1
STP2 0x10 8 Single Tone Profile 2
RP2 0x10 8 RAM Profile 2
STP3 0x11 8 Single Tone Profile 3
RP3 0x11 8 RAM Profile 3
STP4 0x12 8 Single Tone Profile 4
RP4 0x12 8 RAM Profile 4
STP5 0x13 8 Single Tone Profile 5
RP5 0x13 8 RAM Profile 5
STP6 0x14 8 Single Tone Profile 6
RP6 0x14 8 RAM Profile 6
STP7 0x15 8 Single Tone Profile 7
RP7 0x15 8 RAM Profile 7
RAM 0x16 4 RAM

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